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1 ISL54500 +1.8v to +5.5v, 5 , single spdt analog switch ISL54500 the intersil ISL54500 device is a low on-resistance, low voltage, bidirectional, single pole/double throw (spdt) analog switch designed to operate from a single +1.8v to +5.5v supply. targeted applications include battery powered equi pment that benefit from low on-resistance and fast switching speeds (t on =22ns, t off = 15ns). the digital logic input is 1.8v cmos compatible when using a single +3v supply. cell phones, for example, often face asic functionality limitations. the number of analog input or gpio pins may be limi ted and digital geometries are not well suited to analog switch performance. this part may be used to ?mux-i n? additional functionality while reducing asic design risk. the ISL54500 is offered in the 6 ld 1.2mmx1.0mmx0.4mm pitch tdfn package, and 6 ld sot-23 package, alleviating board space limitations. the ISL54500 is a committed spdt that consists of one normally open (no) and one normally closed (nc) switch. this configuration can also be used as a 2-to-1 multiplexer. features ? on-resistance (r on ) -v cc = +5.0v . . . . . . . . . . . . . . . . . . . . . 5.0 -v cc = +3.0v . . . . . . . . . . . . . . . . . . . . . 7.0 -v cc = +1.8v . . . . . . . . . . . . . . . . . . . . . 13 ?r on matching between channels . . . . . . . . . 46m ?r on flatness (+4.5v supply) . . . . . . . . . . . . . 1.1 ? single supply operation . . . . . . . . +1.8v to +5.5v ? fast switching action (+4.5v supply) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns ? guaranteed break-before-make ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . 6kv ? 1.8v, cmos logic compatible (+3v supply) ? available in 6 ld tdfn and 6 ld sot-23 packages ? pb-free available (rohs compliant) applications ? battery powered, handheld, and portable equipment - cellular/mobile phones -pagers - laptops, notebooks, palmtops ? portable test and measurement ?medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? table 1. features at a glance ISL54500 number of switches 1 sw spdt or 2-1 mux 1.8v r on 12 1.8v t on /t off 70ns/52ns 3v r on 6.0 3v t on /t off 30ns/20ns 5v r on 5.0 5v t on /t off 22ns/15ns packages 6 ld tdfn, 6 ld sot-23 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. november 9, 2009 fn6549.2
2 fn6549.2 november 9, 2009 ordering information part number (notes 1, 4) part marking temp. range (c) package (pb-free) (tape and reel) pkg. dwg. # ISL54500iruz-t (note 2) 0 -40 to +85 6 ld tdfn l6.1.2x1.0a ISL54500ihz-t (note 3) 4500 -40 to +85 6 ld sot-23 mdp0038 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termin ation finish, which is rohs compliant and comp atible with both snpb and pb-free soldering operations. intersil pb-fre e products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device in formation page for ISL54500 . for more information on msl please see techbrief tb363 . pin configuration (note 5) ISL54500 (6 ld tdfn) top view ISL54500 (6 ld sot-23) top view note: 5. switches shown for logic ?0? input. 3 2 16 5 4 in v+ gnd no nc com 4 5 6 1 2 3 nc in no gnd v+ com truth table logic pin nc pin no 0onoff 1offon note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions name tdfn pin number sot-23 pin number function v+ 5 4 system power supply input (+1.8v to +5.5v) gnd 2 6 ground connection in 6 2 digital control input com 4 5 analog switch common pin no 1 3 analog switch normally open pin nc 3 1 analog switch normally closed pin ISL54500
3 fn6549.2 november 9, 2009 absolute maximum ratings thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5v input voltages no, nc, in (note 6) . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) output voltages com (note 6) . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) continuous current no, nc, or com. . . . . . . . . . . . 300ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . 500ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . >6kv machine model. . . . . . . . . . . . . . . . . . . . . . . . . . . >200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . .> 2.2kv thermal resistance (typical) ja (c/w) jc (c/w) 6 ld tdfn package (notes 7, 9). . 239.2 111.6 6 ld sot-23 package (note 8, 9) . . 260 120 maximum junction temperature (plastic package). . +150c maximum storage temperature range. . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions v+ (positive dc supply voltage) . . . . . . . . . . . 1.8v to 5.5v analog signal range . . . . . . . . . . . . . . . . . . . . . . 0v to v+ v in (digital logic input voltage (in) . . . . . . . . . . . 0v to v+ temperature range . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. signals on nc, no, in, or com exceeding v+ or gnd are clamped by in ternal diodes. limit forwar d diode current to maximum current ratings. 7. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 8. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 9. for jc , the ?case temp? location is taken at the package top center. electrical specifica tions - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.0v, v inl = 0.8v (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (note 14, see figure 5) 25 - 4.2 5 full - - 6 r on matching between channels, r on v+ = 4.5v, i com = 100ma, v no or v nc = 2.5v (note 14) 25 - 0.046 0.2 full - - 0.3 r on flatness, r flat(on) v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (notes 13, 14) 25 - 1.1 1.3 full - - 1.5 no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 0.3v, 5v, v no or v nc =5v, 0.3v 25 -25 1.2 25 na full -150 - 150 na com on leakage current, i com(on) v+ = 5.5v, v com = 0.3v, 5v, or v no or v nc = 0.3v, 5v, or floating 25 -30 1.7 30 na full -300 - 300 na dynamic characteristics turn-on time, t on v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 22 - ns full - 23 - ns turn-off time, t off v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 15 - ns full - 15 - ns break-before-make time delay, t d v+ = 5.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 3) full - 18 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 16 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz, v com = 1v p-p (see figure 4) 25 - 75 - db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 32 25 - 0.12 - % ISL54500
4 fn6549.2 november 9, 2009 total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l =600 25 - 0.01 - % -3db bandwidth signal = 0dbm, r l = 50 25 - 350 - mhz no or nc off capacitance, c off v+ = 4.5v, f = 1mhz, v no or v nc =v com = 0v (see figure 7) 25 - 6 - pf com on capacitance, c com(on) v+ = 4.5v, f = 1mhz, v no or v nc =v com = 0v (see figure 7) 25 - 12 - pf power supply characteristics power supply range full 1.8 - 5.5 v positive supply current, i+ v+ = 5.5v, v in = 0v or v+ 25 - 0.02 0.1 a full - 0.5 2.5 a digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 2.4 --v input current, i inh , i inl v+ = 5.5v, v in = 0v or v+ full -0.1 0.044 0.1 a electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (note 14, see figure 5) 25 - 6.3 7 full - - 8 r on matching between channels, r on v+ = 2.7v, i com = 100ma, v no or v nc =1.5v (note 14) 25 - 0.05 0.3 full - - 0.4 r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (notes 13, 14) 25 - 1.8 2.3 full - - 2.5 dynamic characteristics turn -on tim e, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 28 - ns full - 30 - ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 20 - ns full - 30 - ns break-before-make time delay, t d v+ = 3.0v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 3) full - 22 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 12 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz, v com = 1v p-p (see figure 4) 25 - 75 - db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 32 25 - 0.4 - % total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 - 0.053 - % -3db bandwidth signal = 0dbm, r l = 50 25 - 350 - mhz no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 6 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 - 12 - pf electrical specifica tions - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.0v, v inl = 0.8v (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units ISL54500
5 fn6549.2 november 9, 2009 power supply characteristics positive supply curre nt, i+ v+ = 3.6v, v in = 0v or v+ 25 - 0.02 - a full - 0.11 - a digital input characteristics input voltage low, v inl full - - 0.5 v input voltage high, v inh full 1.4 --v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -0.1 0.049 0.1 a electrical specifications - 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v inh = 1v, v inl = 0.4v (note 10), unless otherwise specified. parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 1.8v, i com = 10ma, v no or v nc = 0v to v+, (note 14, see figure 5) 25 - 11.9 12.8 full - - 13.8 dynamic characteristics turn -on tim e, t on v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 70 - ns full - 130 - ns turn-off time, t off v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 52 - ns full - 100 - ns break-before-make time delay, t d v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 3) full - 42 - ns charge injection, q v g = 0, r g = 0 , c l = 1.0nf (see figure 2) 25 - 5.8 - pc digital input characteristics input voltage low, v inl full - - 0.4 v input voltage high, v inh full 1 --v notes: 10. v in = input voltage to perform proper function. 11. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established b y characterization and are not production tested. 13. flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal ra nge. 14. limits established by characterizat ion and are not production tested. electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units ISL54500
6 fn6549.2 november 9, 2009 test circuits and waveforms note: logic input waveform is inverted for switches that have the opposite logic sense. note: repeat test for all switches. c l includes fixture and stray capacitance. figure 1a. measurement points figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection figure 3a. measurement points c l includes fixture and stray capacitance. figure 3b. test circuit figure 3. break-before-make time 50% t r < 20ns t f < 20ns t off 90% v+ 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on () + ---------------------------- = switch input logic input v out r l c l com no or nc in 50 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v inh v inl c l v out r g v g gnd com no or nc v+ c logic input in 90% v+ 0v t d logic input switch output 0v v out logic input in com r l c l v out 35pf 50 no nc v+ gnd v nx c ISL54500
7 fn6549.2 november 9, 2009 detailed description the ISL54500 is a bi-directional, single pole/double throw (spdt) analog switch that offers precise switching capability from a si ngle 1.8v to 5.5v supply with low on-resistance (5 ) and high speed operation (t on = 22ns, t off = 15ns). the device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8v), low power consumption (0.11w), low leakage currents (300na max) and small tdfn and sot-23 packages. the low on-resistance and r on flatness provide very low insertion loss and distortion to application that require signal reproduction. external v+ series resistor for improved esd and latch-up immunity intersil recommends adding a 100 resistor in series with the v+ power supply pin of the isl54050 ic (see figure 8). during an overvoltage transient event (such as occurs during system level iec 61000 esd testing), substrate currents can be generated in the ic that can trigger parasitic scr structures to turn on, creating a low impedance path from the v+ power supply to ground. this will result in a significant amount of current flow in the ic, which can potentially create a latch-up state or permanently damage the ic. the external v+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many over voltage transient events. under normal operation, the sub-microamp i dd current of the ic produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance. figure 4. off-isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) analyzer r l signal generator v+ c 0v or v+ no or nc com in gnd v+ c v inl or v inh no or nc com in gnd v nx v 1 100ma r on = v 1 /i 1 * i 1 * i 1 = 10ma at v+ = 1.8v 0v or v+ analyzer v+ c no or nc signal generator r l gnd in 1 com nc or no 50 v+ c gnd no or nc com in impedance analyzer v inl or v inh ISL54500
8 fn6549.2 november 9, 2009 supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 9). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the v+ rail. logic inputs can easily be protected by adding a 1k resistor in series with the input (see figure 9). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins (as shown in figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current. power-supply considerations the ISL54500 construction is typical of most single supply cmos analog switches, in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 4v maximum supply voltage, the ISL54500 5.5v maximum supply voltage provides plenty of room fo r the 10% tolerance of 3.6v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.8v but the part will operate with a supply below 1.8v. it is important to note that the in put signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the ?electrical specifications? tables starting on page 3 and the ?typical performance curves? starting on page 9 for details. v+ and gnd also power the internal logic and level shifters. the level shifters convert the input logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this family of switches cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. logic-level thresholds this switch family is 1.8v cmos compatible (0.5v and 1.4v) over a supply range of 2v to 3.6v (see figure 16). at 3.6v the v ih level is about 0.98v. this is still below the 1.8v cmos guaranteed high output minimum level of 1.4v, but noise margin is reduced. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 systems, the ISL54500 has a -3db bandwidth of 350mhz (see figure 17). the frequency response is figure 8. v+ series resistor for enhanced esd and latch-up immunity in com 100 v+ gnd c optional protection resistor nc no figure 9. overvoltage protection gnd v com v nx v+ in x optional protection resistor optional schottky diode optional schottky diode ISL54500
9 fn6549.2 november 9, 2009 very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off-isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. figure 18 details the high off-isolation provided by this family. at 1mhz, of-isolation is about 75db in 50 systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off-isolation due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog-signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. typical performance curves t a = +25c, unless ot herwise specified figure 10. on-resistance vs supply voltage vs switch voltage figure 11. on-resistance vs switch voltage figure 12. on-resistance vs switch voltage f igure 13. on-resistance vs switch voltage r on ( ) v com (v) 012345 0 1 2 3 4 5 6 7 8 i com = 100ma v+ = 2.7v v+ = 3v v+ = 4.5v v+ = 5v r on ( ) v com (v) 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v+ = 4.5v i com = 100ma +25c +85c -40c 6 r on ( ) v com (v) 2 3 4 5 6 7 8 0 0.5 1.0 1.5 2.0 2.5 v+ = 2.7v i com = 100ma +25c +85c -40c r on ( ) v com (v) 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v+ = 1.8v i com = 10ma +25c +85c -40c ISL54500
10 fn6549.2 november 9, 2009 figure 14. turn-on time vs supply voltage f igure 15. turn-off time vs supply voltage figure 16. digital switching point vs supply voltage figure 17. frequency response typical performance curves t a = +25c, unless ot herwise specified (continued) t on (ns) 10 20 30 40 50 60 70 80 90 100 110 120 130 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 +25c -40c +85c v+ (v) t off (ns) v+ (v) 0 10 20 30 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 +25 c -40 c +85 c v+ (v) v inh and v inl (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v inh v inl frequency (hz) normalized gain (db) 100k 1m 10m 100m 1g -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 v+ = 1.8v to 5.5v v com = 1v p-p ISL54500
11 fn6549.2 november 9, 2009 die characteristics substrate potential (powered up): gnd transistor count: process: submicron cmos figure 18. off-isolation figure 19. charge injection vs switch voltage typical performance curves t a = +25c, unless ot herwise specified (continued) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 1k 10k 100k 1m 10m 100m 1g frequency (hz) (db) v+ = 1.8v to 5.5v v com (v) -6 -1 4 9 14 19 0.00.51.01.52.02.53.03.54.04.55.0 v+ = 3v v+ = 1.8v v+ = 5v q (pc) ISL54500
12 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6549.2 november 9, 2009 for additional products, see www.intersil.com/product_tree sot-23 package family e1 n a d e 4 3 2 1 e1 0.15 d c 2x 0.20 c 2x e b 0.20 m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 0 +3 -0 gauge plane a mdp0038 sot-23 package family symbol millimeters tolerance sot23-5 sot23-6 a 1.45 1.45 max a1 0.10 0.10 0.05 a2 1.14 1.14 0.15 b 0.40 0.40 0.05 c 0.14 0.14 0.06 d 2.90 2.90 basic e 2.80 2.80 basic e1 1.60 1.60 basic e 0.95 0.95 basic e1 1.90 1.90 basic l 0.45 0.45 0.10 l1 0.60 0.60 reference n 5 6 reference rev. f 2/07 notes: 15. plastic or metal protrusions of 0.25mm maximum per side are not included. 16. plastic interlead protrusions of 0.25mm maximum per side are not included. 17. this dimension is measured at datum plane ?h?. 18. dimensioning and tolerancing per asme y14.5m-1994. 19. index area - pin #1 i.d. will be located within the indicated zone (sot23-6 only). 20. sot23-5 version has no center lead (shown as a dashed line). ISL54500
13 fn6549.2 november 9, 2009 ISL54500 ultra thin dual flat no-l ead plastic package (utdfn) b d a e 0.10 c 2x pin 1 top view 0.10 c 2x reference detail a 0.10 c 0.08 c 7x a3 a1 a c seating plane 5x l e 1 3 64 4x bottom view side view 0.10 cab 0.05 c b6x note 3 l1 detail a detail b pin 1 lead 0.1x45 chamfer detail b a3 a1 1.40 land pattern 1.00 0.30 0.35 0.20 0.45 0.40 0.20 10 l6.1.2x1.0a 6 lead ultra thin dual flat no-lead plastic package symbol millimeters notes min nomi- nal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 0.95 1.00 1.05 - e 1.15 1.20 1.25 - e 0.40 bsc - l 0.30 0.35 0.40 - l1 0.40 0.45 0.50 - n 6 2 ne 3 3 0-12 4 rev. 2 8/06 notes: 1. dimensioning and tolerancing conform to asme y14.5- 1994. 2. n is the number of terminals. 3. ne refers to the number of terminals on e side. 4. all dimensions are in millimet ers. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see in tersil technical brief tb389.

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